This application is based upon and claims priority of Japanese Patent Application No. 11-110061, the contents being incorporated herein by reference.
The present invention generally relates to a testing method of a probe card for simultaneously testing, in the wafer condition, a plurality of chips and chip size packages (hereinafter referred to as CSP) formed on the wafer and of semiconductor devices such as a wafer having formed chips or a wafer level CSP or the like.
A new type of semiconductor package has been proposed (Japanese Published Unexamined Patent Application No. HEI 10-79362, U.S. patent application No. 09/029,608). This semiconductor package has a structure that an external output terminal formed by a bump electrode on a chip is provided in order to have the shape of a semiconductor device to follow a semiconductor element (hereinafter referred to as chip) as much as possible, wherein the side surface of at least a bump electrode is resin-sealed in the wafer condition and thereafter such wafer is cut to each chip.
On the occasion of testing this semiconductor device, a more effective testing can be realized by conducting the test at a time in the wafer condition, in place of individually conducting the testing for each CSP after the cutting. It is also true in the wafer where a plurality of ordinary chips are formed. The present invention relates to the testing method of a probe card and a semiconductor device to conduct the testing to each chip in the wafer condition where a plurality of chips and CSPs are formed.
FIG. 1 to FIG. 3 illustrate an example of a CSP in the related art. FIG. 1 is a cross-sectional view thereof, FIG. 2 illustrates the condition of the CSP of FIG. 1 before it is cut into individual CSPs and FIG. 3 is a plan view of FIG. 2.
The CSP illustrated in FIG. 1 is covered with a silicon nitride film 2 at the area other than the aluminum pad 4 on the chip 1 and moreover a polyimide layer 3 is also formed thereon. The aluminum electrode pad 4 formed on the chip is too narrow for a prober to make contact during the testing time under this arrangement and it is also a problem that mounting on the mounting substrate is impossible during the mounting process. Therefore, a re-wiring layer 5 is formed on the polyimide layer 3, and is extended to adequate positions on the chip and is then connected to a copper bump electrode 6 and an interval of the aluminum pad 4 is widened. For the mounting on the mounting substrate, a solder ball 8 is formed on the copper bump electrode 6 via a barrier metal layer 7.
At the time of manufacturing the CSP of FIG. 1, after the copper bump electrode 6 is formed on the wafer, a resin layer 9 is formed to seal at least the side surface of the copper bump electrode 6. Thereafter, a solder ball 8 is formed and the wafer is then cut into individual pieces along the dicing line 12 as illustrated in FIG. 2.
However, at the time of testing the CSP, testing efficiency becomes bad after the wafer is cut into individual chips. Therefore, it is requested to conduct the testing under the condition illustrated in FIG. 3 before the cutting process.
FIG. 3 illustrates the condition where the CSP is formed in the wafer condition and the wafer 11 is held by a tape 10. If it is attempted to apply the prober formed of the existing stylus to the electrode pad (not illustrated) of each chip, it is very difficult to apply the stylus because the pad interval is too narrow.
A method for testing the chip having a narrow pad interval is described as an example in the Japanese Published Unexamined Patent Application No. HEI 7-263504. In this method, a contact corresponding to the pad position of the chip is formed on the flexible sheet and it is then pushed to the pad of the chip with negative pressure to establish the contact.
However, the above reference HEI 7-263504 has a problem illustrated in FIG. 4 as the problem which has not yet been recognized.
When the method introduced in the above reference is tried to be applied to the testing of a wafer condition, the wafer testing is conducted utilizing a probe card where a contact electrode is formed, at the position corresponding to each chip on the wafer 11, on the contact board 13. When the contact board 13 is closely in contact with the wafer 11 by applying a negative pressure during the testing, a problem arises that the solder ball 8a at the end part is placed in contact with the contact board but the contact board is floated at the area of solder ball 8b in the central area, losing contact condition thereof.
Moreover, also generated is a problem that the balls at the end part are deformed more easily when the solder balls at the end part are pressed.
In addition, it is generated as a problem that since the contact board is pulled with unequal forces, the sheet is elongated at the local areas.
Moreover, due to the difference of thermal expansion coefficient of the wafer and the sheet, both electrode positions are deviated to a large extent as it goes to the end part and thereby a problem of contact failure may be generated between the center and end part of the sheet.
In addition, the signal leads must be extended to the external side from the electrode of the contact board but there exists a fear for breakdown of the signal lead because the sheet becomes wavy.
The above problems are generally generated not only during the testing of the CSP in the wafer condition but also during the testing of the wafer where a plurality of chips are formed in the wafer condition.
Therefore, it is an object of the present invention to provide a testing probe card for a semiconductor device, which can always assure an excellent contact condition between electrodes of each chip or electrode pads of a CSP on the occasion of testing a chip or a CSP in the wafer condition.
It is a further object of the present invention to solve the problem that contact failure may be generated between the center and end part of the sheet where both electrode positions are deviated to a large extent as it goes to the end part and thereby due to the difference of thermal expansion coefficient of the wafer and sheet.
It is a further object of the present invention to solve the problem that there exists a fear for breakdown of a signal lead because the sheet becomes wavy where the signal leads are extended to the external side from the electrode of the contact board.
It is further object of the present invention to provide a test method of a semiconductor device under circumstances of the excellent contact condition between electrodes of each chip or electrode pads of each CSP on the occasion of testing a chip or a CSP in the wafer condition.
Objects of the invention are achieved by a probe card for testing a plurality of semiconductor devices on a wafer comprising a contact board having a flexibility, a plurality of groups of contact electrodes provided on the contact board, a rigid base having openings exposing the groups of the contact electrodes on the contact board, and a wiring connecting to a predetermined contact electrode.
In the present invention described above, the probe card operates such that the rigidity of the probe card as a whole is maintained by a rigid base and flexibility is given to the contact electrode on the contact board in the area corresponding to the aperture.
Moreover, since the contact board within the aperture is flexible, if heights of bumps on the wafer fluctuate a little, fluctuation of bumps are absorbed by the flexible contact board and thereby contact failure is never generated. In addition, since the rigid base is formed like a lattice, it moves more easily in the thickness direction of the wafer than the plate type one having no aperture and the contact failure due to uneven bump height is difficult to occur from this viewpoint.
Further, since respective contact electrodes on the contact board corresponding to each chip are isolated due to the existence of the rigid base, distortion resulting from mismatching of thermal expansion coefficients of the wafer and the contact board is never accumulated in the periphery of the wafer as positional displacement to the contact electrode in the neighboring area and thereby contact in the same condition can be realized in any position on the wafer.
Further objects of the invention are achieved by a test method of a plurality of semiconductor devices on a wafer comprising the steps of preparing a probe card including a contact board having a flexibility, a plurality of groups of contact electrodes provided on the contact board, a rigid base having openings exposing the groups of the contact electrodes on the contact board and a wiring connecting to a predetermined contact electrode, contacting the contact electrode and an electrode on the semiconductor device by adhering the contact electrode to the wafer and testing the semiconductor devices via the wiring.
In the present invention described above, the semiconductor device testing method provides the operation that since the probe card used has an aperture and the contact board in the aperture is flexible, even if a height of bumps on the wafer is a little fluctuated, such fluctuation of bumps can be absorbed by the flexible contact board and the wafer can be tested without generation of contact failure. In addition, since the rigid base is formed in the shape of a lattice, it can move more easily in the thickness direction of wafer than the plate type having no aperture and contact failure due to uneven bump height is difficult to occur even in this viewpoint.
Further, since respective contact electrodes on the contact board corresponding to each chip are isolated due to existence of a rigid base, distortion resulting from mismatching of thermal expansion coefficients of the wafer and contact board is never accumulated in the periphery of the wafer as positional displacement to the contact electrode in the neighboring area and thereby contact in the same condition for wafer testing can be realized in any position on the wafer.